Features Model TechnologyÆs V-System 1076-1993/1164 compliant VHDL
simulator integrated with SynarioÆs Project Navigator environment,
simplifying the design process
Direct compile technology ensures fast compilation and high
performance simulation taking advantage of machine-independent object code,
saving design time
Multiple, dynamically linked windows enable rapid exploration
and debug of design, increasing productivity
Interactive waveform display supports fast and easy simulation
and analysis
Dataflow diagnostic tool enables analysis of inputs and outputs,
making it easy to tracing signals through all levels of hierarchy
Integration enables timing simulation with easy access to semiconductor
vendor timing models, ensuring accurate design performance
ôWhat ifö simulation supports investigation of functional alternatives
without changing original stimulus file, saving time and effort
Verilog Simulator
Features Avant!Æs OVI compliant, high performance multi-level Verilog
simulation engine integrated within SynarioÆs Project Navigator environment,
simplifying the design process
Gate-level engine handles three times the capacity of Verilog-XL
with significantly enhanced performance
Interpreted engine facilitates interactive debugging with fast
turnaround between coding and simulation runs for improved productivity
Automatic model generation for all supported device architectures
eliminates need to specify libraries and models, ensuring fast and easy
design verification
Logic-analyzer-like waveform viewer provides flexible results
viewing, and updates every time you single step the simulator
Cross-probing between schematic and waveform viewer tie simulation
results directly to the source design, making results easier to interpret
Interactive debugging provides force/preset/monitor access to
all of the designÆs signals, for fast and easy, on-the-fly changes
Full timing simulation with delay-annotated models provides
comprehensive support for timing problems in routed devices
Verilog-Pro Simulator
Adds advanced simulation capabilities to SynarioÆs Verilog Simulator
supporting behavioral, RTL, and gate-level constructs for multi-level design
verification
Powerful user interface features source-level debugger, register
display, signal backtracker, timing violation markers, and syntax error
tracer/editor, simplifying verification tasks
Additional standards support for Programming Language Interface
(PLI), and Standard Delay Format (SDF), enhancing Verilog-based design
support
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